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Paper Details

Paper Title
Design of Low Power Phase Locked Loop using Current Starved Voltage Controlled Oscillator
Abstract
This work is based on design of low power PLL with the help of CSVCO. The conventional voltage control oscillator will take more power as compare to CSVCO. VCO is the major part of PLL circuit and it affects the system performance in terms of power consumption and noise performance. In modern VCO design power consumption and high output frequency range have become important performance metrics .To design PLL proposed circuit will replace PLL with CSVCO .Because the VDD varies ±10% of 1.8V i.e from 1.62V to 1.98V.For this voltage variation the ring architecture produces an output frequency from 4.175GHz to 5.077GHz with the difference of 992 MHz, which is large variation. The output frequency is not stable when it is dependent on VDD. In most of the application PLL are used for clock and data recovery purpose to achieve this the CSVCO will use. This CSVCO is applicable for PLL application such as clock generation and recovery, frequency synthesizer, fast locking in digital circuit etc. The proposed circuit area and power consumption are very less and compatible for PLL application. The circuit analysis is performed and respective wave form are generated at 1MHz and power gain estimation at1GHz is 33.22E-6 is obtained with supply voltage of 1V. All the generated wave form are analyzed by using Cadence Virtuoso Gpdk045nm CMOS technology.
Keyword
Phase Locked Loop, Current Starved Voltage Control Oscillator, and Voltage Control Oscillator.
Others Details
Paper Id : 20978
Author Name : Jagbandhan kindo
Co-Author Name(s) : K.Bapayya
Volume/Issue No : Volume 04 Issue 10
Page No : 54-60
DOI Number : DOI:10.21090/IJAERD.20978
License : This work is licensed under a Creative Commons Attribution 4.0 International License.
website : http://www.ijaerd.com/index.php
Impact Factor : 5.71, SJIF-2017
ISSN Details : eISSN: 2348-4470, pISSN:2348-6406
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