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Paper Details

Paper Title
Design of DPLL and Implementation of BIST to Evaluate its Characteristics
Abstract
All digital systems need to synchronize between Integrated Circuits and functional blocks, mainly to progress digital systems operations for excellence in performance. Future processors need to work with different ICs and IPs, whose operating speed is different; there is requirement for high speed clocks. This has to be done by just using the low frequency on board clock. To generate the on-chip clocks to have well-timed, Phase locked-loops (PLLs) are used. But designing a fully digital PLL is needed because all the designs are digital and analog component will need more power and will reduce efficiency. Most of the traditional PLL are monolithic design with other circuits. The proposed DPLL is just based on counters, dividers and digital phase lock detectors which are easy to fabricate when compared to analog component and can be integrated in any system easily. It can generate wide range of frequencies and has in built BIST to test the operation of PLL and to determine characteristics like lock time, jitter and duty cycle. The experimental results of DPLL with waveforms are shown for 50 MHz reference clock signal to generate 200 MHz clock DPLL. BIST for the PLL is implemented using TESSENT TOOL.
Keyword
DPLL, BIST, TESSENT, PLL, DCO, JTAG, TAP, DTAB.
Others Details
Paper Id : 25463
Author Name : PANCHETI HAREESH
Co-Author Name(s) : SIMHADRI VENKATA ABHISHEK
Volume/Issue No : Volume 04 Issue 11
Page No : 122-128
DOI Number : DOI:10.21090/IJAERD.25463
License : This work is licensed under a Creative Commons Attribution 4.0 International License.
website : http://www.ijaerd.com/index.php
Impact Factor : 5.71, SJIF-2017
ISSN Details : eISSN: 2348-4470, pISSN:2348-6406