Call for papers :

Submission Last Date 28/02/2018
Status Notification Within 2 Days
Submit Paper Online

Check Paper Status

Paper Status

News & Updates

IJAERD provides Hard Copy of Published Certificates of Publication to each author.

We have started accepting articles by online means directly through website. Article submission link is given on left side

IJAERD Provide Review card, Acceptance Letter and Fee Receipt without taking any extra charges

IJAERD invites research paper from various engineering disciplines for Vol.1 Issue 12 (Dec. - 2014) issue,

Conference Proceedings

National Conference on Emerging Trends in Computer & Electrical Engineering (ETCEE - 2014) March 7-8, 2014, Organized by Atmiya Institute of Technology and Science, Rajkot

National Conference on Recent Research in Engineering and Technology (NCRRET-2015) organizing by Dr. Jivraj Mehta Institute of Technology, Mogar-Anand

National Conference on Emerging Trends in Computer, Electrical & Electronics (ETCEE - 2015), March 13-14, 2015, Organized by Atmiya Institute of Technology and Science, Rajkot

Paper Details

Paper Title
Floating-point butterfly architecture based on redundant number system and Fused-Dot-Product-Add unit
The Fast Fourier transforms (FFT) plays a major role in ruling the performance of many communication systems. The butterfly unit is the major building block of FFT architectures which mainly consists of addition and multiplication operations over complex numbers. The number representation plays an important role in enhancing the speed of any digital system. The strings of digits can be represented using floating-point (FP) arithmetic or fixed-point to design butterfly unit. The FP arithmetic provides a wide dynamic range by reducing the design constraints like scaling and overflow/underflow, but it has low performance issues in terms of speed when compared to fixed-point representation. The fused-dot-product-add (FDPA) unit based on binary sign digit representation (BSD) is used to increase the speed of FP butterfly architecture; it is used to compute AB±CD±E. The FDPA unit consists of FP BSD multiplier and FP BSD three-operand-adder units that use a BSD carry-limit adder. FP three-operand adder using comparator is proposed to reduce the area and delay of the FDPA unit and a new BSD adder is further proposed to increase the speed of the existing architectures. The simulations of the architectures in this paper are done by using Xilinx software for efficient results.
butterfly unit, fixed-point, floating-point, binary sign digit representation, redundant number system.
Others Details
Paper Id : 25562
Co-Author Name(s) : Ch.Jaya PrakashDr PHS Tejo murthy
Volume/Issue No : Volume 04 Issue 11
Page No : 60-66
DOI Number : DOI:10.21090/IJAERD.25562
Publication Date : 2017-11-09
License : This work is licensed under a Creative Commons Attribution 4.0 International License.
website :
Impact Factor : 4.72, SJIF-2016
ISSN Details : eISSN: 2348-4470, pISSN:2348-6406