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Paper Details

Paper Title
Floating-point butterfly architecture based on redundant number system and Fused-Dot-Product-Add unit
Abstract
The Fast Fourier transforms (FFT) plays a major role in ruling the performance of many communication systems. The butterfly unit is the major building block of FFT architectures which mainly consists of addition and multiplication operations over complex numbers. The number representation plays an important role in enhancing the speed of any digital system. The strings of digits can be represented using floating-point (FP) arithmetic or fixed-point to design butterfly unit. The FP arithmetic provides a wide dynamic range by reducing the design constraints like scaling and overflow/underflow, but it has low performance issues in terms of speed when compared to fixed-point representation. The fused-dot-product-add (FDPA) unit based on binary sign digit representation (BSD) is used to increase the speed of FP butterfly architecture; it is used to compute AB±CD±E. The FDPA unit consists of FP BSD multiplier and FP BSD three-operand-adder units that use a BSD carry-limit adder. FP three-operand adder using comparator is proposed to reduce the area and delay of the FDPA unit and a new BSD adder is further proposed to increase the speed of the existing architectures. The simulations of the architectures in this paper are done by using Xilinx software for efficient results.
Keyword
butterfly unit, fixed-point, floating-point, binary sign digit representation, redundant number system.
Others Details
Paper Id : 25562
Author Name : KONDAMURI RAJI
Co-Author Name(s) : Ch.Jaya PrakashDr PHS Tejo murthy
Volume/Issue No : Volume 04 Issue 11
Page No : 60-66
DOI Number : DOI:10.21090/IJAERD.25562
License : This work is licensed under a Creative Commons Attribution 4.0 International License.
website : http://www.ijaerd.com/index.php
Impact Factor : 5.71, SJIF-2017
ISSN Details : eISSN: 2348-4470, pISSN:2348-6406