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Paper Details

Paper Title
Design & Comparison of Low Power 64 Bit ALU using CMOS and Transmission gate Logic
Abstract
Arithmetic and logical unit (ALU) is an important block of microprocessor. Now days for most of the applications of digital circuits the important attributes are minimizing power consumption and area whreas maximizing speed. The main aim of this project is to design 64 bit ALU with less number of transistors using fast complementary metal oxide semiconductor logic and Transmission gate logic. The Arithmetic and Logical Unit (ALU) is designed to perform all the Arithmetical and Logical operations, including bit shifting operation which is needed to be done for almost any data that is being processed by the Central Processing Unit (CPU). The proposed 64 bit ALU is designed and simulated in Cadence Virtuoso Tools in GPDK 45nm Technology.
KeyWord
CMOS, ALU, Adders, Multiplexers, Subtractors, Transmission gate & all basic gates.
Others Details
Paper Id : 68188
Author Name : Mangali Amarnath
Co-Author Name(s) : Sridhar Cherala
Volume/Issue No : Volume 04 Issue 10
Page No : 126-134
DOI Number : DOI:10.21090/IJAERD.68188
Publication Date : 2017-10-12
License : This work is licensed under a Creative Commons Attribution 4.0 International License.
website : http://www.ijaerd.com/index.php
Impact Factor : 4.72, SJIF-2016
ISSN Details : eISSN: 2348-4470, pISSN:2348-6406