Design and Analysis of a New Loadless 4T SRAM Cell with 32nm CMOS Technology

Abstract

A significantly large segment of modern system on chips (SoCs) is occupied by Static Random Access
Memory (SRAM). The goal of this paper is to reduce power and less area of SRAM. Here two different configurations of
SRAM cell are designed and analysed. The standard six-transistor (6T) SRAM cell and a new loadless four transistor
(4T) SRAM cell are designed using 32nm CMOS technology. Here the various configurations of SRAM cells are
designed, 1-Bit, 16-Bit, 64-Bit and 1-Kb using both 6T SRAM cell and a new loadless 4T SRAM cell using 32nm CMOS
technology for checking its functionality: power dissipation, area occupancy, read access time and write access time.
Compared to 6T SRAM array, the new loadless 4T SRAM array consumes less power and requires less area.