DESIGN OF LOW POWER PULSE TRIGGERED DUAL DYNAMIC FLIP FLOP BASED ON A SIGNAL FEED-THROUGH SCHEME

Authors

  • S. KEERTHANA Assistant Professor, Department of ETE, Karpagam College of Engineering, Coimbatore
  • R. ARIGOVINDAN Assistant Professor, Department of ECE, Panimalar Polytechnic College, Chennai
  • J. VASANTHARAJ PG Graduate, Department of ECE, Tiruchengode

Keywords:

Flip-flop (FF), Low Power, Explicit Pulse Triggered Flip Flop, Signal Feed-Through Scheme, Dual Dynamic FlipFlop

Abstract

Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular,
digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register
file, Dual Dynamic Flip-Flop Based on a Signal Feed-Through Scheme, and first infest out. A low-power flip-flop (FF)
design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal
feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in
conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based
on post-layout simulation results using cadence CMOS 180-nm technology, the proposed design outperforms the
conventional P-FF design data-close-to-output (MHLFF) by 8.2% in data-to-Q delay. In the meantime, the performance
edges on power and power- delay-product metrics are 24.6% and 31.7%, respectively.

Published

2016-04-25

How to Cite

S. KEERTHANA, R. ARIGOVINDAN, & J. VASANTHARAJ. (2016). DESIGN OF LOW POWER PULSE TRIGGERED DUAL DYNAMIC FLIP FLOP BASED ON A SIGNAL FEED-THROUGH SCHEME. International Journal of Advance Engineering and Research Development (IJAERD), 3(4), 309–315. Retrieved from https://ijaerd.com/index.php/IJAERD/article/view/1365