High Speed Vedic Multiplier Based Review with its Proposed Implementation for Parallel FIR Filter

Abstract

The performance of any processor depends upon its speed, area and delay. Multiplier play important role in any
digital design. In Digital Signal Processor (DSP) application multiplier is main and essential functional block. Conventional
multiplication process requires more iteration and hence more time for operation. To improve the performance of the
processor its speed, area and power consumption need to be improved. Many researchers have been trying to design
multipliers offering high speed, low power consumption, less area in one multiplier thus making it suitable for various high
speed, low power application. For many DSP applications processors speed is the major concerned parameter compared to
other useful parameters like area and power. Vedic mathematics is an ancient mathematics that has a unique method of
computation based on simple rule. Urdhva Tiryagbhyam algorithm of Vedic mathematics is applicable for all case of
multiplication. This paper reviews Vedic mathematics based high speed multiplier for Finite Impulse Response (FIR) filter
design. The Digital filter design using Vedic mathematics in Field Programmable Logic Array (FPGA) facilitates high speed
as compared to conventional method and other algorithm.