Design of Pipelined ADC for High Speed Application

Authors

  • Shivani R. Patel PG Student Electronic & Communication, LCIT-Bhandu Gujarat Technological University, Gujarat, India
  • Priyesh P. Gandhi Assistant Professor, L.C. Institute of Technology Bhandu, Mehasana, Gujarat, India

Keywords:

Pipeline, High Speed, ADC

Abstract

This paper describes the implementation of a 8-bit 500 MS/s pipelined ADC using a conventional 0.18μm
CMOS technology in Tanner EDA Tool. Two-stage OPAMP topology is used after Sample and hold block for improving
the settling performance and in residue amplification. The supply voltage for this Pipelined ADC is 1.8 V. The simulation
result shows speed of 0.5 GHz achieved with input frequency of 1 MHz and power dissipation of 169mW.

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Published

2015-04-25

How to Cite

Shivani R. Patel, & Priyesh P. Gandhi. (2015). Design of Pipelined ADC for High Speed Application. International Journal of Advance Engineering and Research Development (IJAERD), 2(4), 483–489. Retrieved from https://ijaerd.com/index.php/IJAERD/article/view/676

Issue

Vol. 2 No. 4 (2015): Volume 2 Issue 4, April 2015

Section

Articles