Design of Pipelined ADC for High Speed Application


  • Shivani R. Patel PG Student Electronic & Communication, LCIT-Bhandu Gujarat Technological University, Gujarat, India
  • Priyesh P. Gandhi Assistant Professor, L.C. Institute of Technology Bhandu, Mehasana, Gujarat, India


Pipeline, High Speed, ADC


This paper describes the implementation of a 8-bit 500 MS/s pipelined ADC using a conventional 0.18μm
CMOS technology in Tanner EDA Tool. Two-stage OPAMP topology is used after Sample and hold block for improving
the settling performance and in residue amplification. The supply voltage for this Pipelined ADC is 1.8 V. The simulation
result shows speed of 0.5 GHz achieved with input frequency of 1 MHz and power dissipation of 169mW.



How to Cite

Shivani R. Patel, & Priyesh P. Gandhi. (2015). Design of Pipelined ADC for High Speed Application. International Journal of Advance Engineering and Research Development (IJAERD), 2(4), 483–489. Retrieved from