All Digital Phase Locked Loop with High DCO resolution

Authors

  • Kunjal Parmar Vishwakarma Government Engineering College, Chandkheda, Ahmedabad
  • Kirit Patel Vishwakarma Government Engineering College, Chandkheda, Ahmedabad
  • Alpesh Patel Vishwakarma Government Engineering College, Chandkheda, Ahmedabad

Keywords:

All digital phase locked loop (ADPLL), Phase locked loop (PLL), Digital control oscillator (DCO),phase frequency detector(PFD)

Abstract

In this paper we propose a very high-resolution all digital phase locked loop (ADPLL). ADPLL is designed with
the cell library and described in hardware description language (HDL). We design a digital controlled oscillator with 1.06
ps resolution for phase frequency detector minimized up to 5ps. So this ADPLL is suitable for system on chip application.

Published

2015-05-25

How to Cite

Kunjal Parmar, Kirit Patel, & Alpesh Patel. (2015). All Digital Phase Locked Loop with High DCO resolution. International Journal of Advance Engineering and Research Development (IJAERD), 2(5), 160–164. Retrieved from https://ijaerd.com/index.php/IJAERD/article/view/787