A Low-Power Single-Phase Dual-Modulous Prescaler


  • Mehul R. Soni PG Student, Electronics & Communication Department LCIT-Bhandu College, GTU, Gujarat, India
  • Nilesh D. Patel Assistant Professor, Electronics & Communication Department LCIT-Bhandu College, Mehsana, Gujarat, India


Very Large Scale Integration(VLSI), CMOS, Prescaler, Swallow Counter, Program Counter, Wireless LAN(WLAN), Phase Lock Loop(PLL), Source Coupled Logic(SCL), True Single Phase Clock(TSPC), Extended True Single Phase Clock(E-TSPC), Phase Frequency Detector(PFD), Bluetooth, Zigbee


— In this paper, a wideband 2/3 prescaler is verified in the design of proposed wide band multimodulus
32/33/47/48 prescaler. A dynamic logic multiband flexible integer-N divider is designed which uses the wideband 2/3
prescaler, multimodulus 32/33/47/48 prescaler. Since the multimodulus 32/33/47/48 prescaler has maximum operatin g
frequency of 6.2 GHz, the values of Program (P) and Swallow(S) counters can actually be programmed to divide over the
whole range of frequencies. However, the P and S counters are programmed accordingly. The proposed multiband
flexible divider also uses an improved loadable bit-cell for Swallow - counter and consumes a power of 0.96 and 2.2 mW,
respectively, and provides a solution to the low power PLL synthesizers for Bluetooth, Zigbee, IEEE 802.15.4, and IEEE
802.11a/b/g WLAN applications with variable channel spacing.



How to Cite

Mehul R. Soni, & Nilesh D. Patel. (2015). A Low-Power Single-Phase Dual-Modulous Prescaler. International Journal of Advance Engineering and Research Development (IJAERD), 2(5), 646–649. Retrieved from https://ijaerd.com/index.php/IJAERD/article/view/972